Methods of manufacturing mosfet devices

ABSTRACT

Example methods of manufacturing MOSFET devices are disclosed. One example method may include an oxidation, an etching, an ion implanting for a threshold voltage control to form an elevated source/drain region and thereby implements an ultra shallow junction.

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and, moreparticularly, to methods of manufacturing metal oxide semiconductorfield effect transistor (MOSFET) devices.

BACKGROUND

[0002] Generally, a gate of a MOSFET device is composed of a polysiliconmaterial. Polysilicon is used because it satisfies a material featurerequired for a gate material, such as a high melting point, ease informing a thin film and a line pattern, stability in an acidicenvironment, and a conformal surface thereof. Additionally, in an actualMOSFET device, the gate made of the polysilicon shows a low resistancebecause it contains a dopant such as, for example, phosphorous, arsenic,and/or boron.

[0003] However, as a level of integration of the MOSFET increases, thereare limitations and drawbacks for implementing a resistance that isrequired between a narrow linewidth.

[0004] Using a conventional method for manufacturing a MOSFET device, itis difficult to form an ultra shallow junction that is required to ahighly integrate MOSFET devices. Therefore, MOSFET fabrication requiresa process technology to form an elevated source/drain region. Further, acontrol of a threshold voltage cannot be stabilized in the MOSFET devicedue to transformation of an implanted dopant array by an accompanyingheat process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIGS. 1A to 1H illustrate an example disclosed procedure formanufacturing MOSFET devices.

DETAILED DESCRIPTION

[0006] Referring to FIG. 1A, a shallow trench isolation (STI) 12 isselectively formed in an upper portion of a silicon substrate 10.

[0007] Referring to FIG. 1B, after a surface of an active area of thesubstrate 10 is oxidized to form an oxide layer 14, a dopant is lightlyimplanted to thereby form a lightly doped drain (LDD) around the activearea of the substrate 10. Herein, a density of LDD can be varied.

[0008] Referring to FIG. 1C, a nitride layer 16 is deposited on anentire surface of a structure of FIG. 1B. Areas of the nitride layer 16and the oxide layer 14 where a gate will be located are removed, and thesubstrate 10 corresponding to the area is also etched by a predetermineddepth. Herein, the substrate 10 is etched by about 200 angstroms to 1000angstroms in depth so that a hole for the gate is formed.

[0009] Referring to FIG. 1D, the exposed portion of the substrate 10 inthe hole for the gate is oxidized at about 600 to 800° C. to form anoxide layer 18 having a thickness of about 100 angstroms. Ions are thenimplanted through the oxide layer 18 into the substrate 10. The oxidelayer 18 prevents the substrate 10 from being damaged during the ionimplanting for control of a threshold voltage.

[0010] Referring to FIG. 1E, the oxide layer 18 is removed and a gateinsulating layer 20 is deposited over all the surface of the structure.Then the hole of the structure is filled with a polysilicon 22.

[0011] Referring to FIG. 1F, a chemical mechanical polishing process isperformed until the nitride layer 16 is exposed. In the result, apolysilicon gate 23 filling the hole for the gate is formed.

[0012] Referring to FIG. 1G, the nitride layer 16 is removed by a wetetch and then an oxide layer 24 is formed thereon. Thereafter, a nitridelayer is deposited on the oxide layer 24 and then etched back to form agate sidewall 26 around the polysilicon gate 23.

[0013] Referring FIG. 1H, ions are implanted to form a source 28 and adrain 30 at both sides of the polysilicon gate 23 and the oxide layer 24exposed by the etch back is removed to complete a MOSFET device.

[0014] As described above, an ultra shallow junction may be forming byelevating a source/drain region. The disclosed process may be used tomanufacture a non-volatile memory device that is appropriate to form aself-align flash memory.

[0015] As disclosed herein, one example method may include (a)selectively forming a shallow trench isolation in a substrate; (b)forming a first oxide layer on a surface of an active region of thesubstrate and implanting ions thereinto for forming a low doped drain inthe active region; (c) forming a nitride layer; (d) removing a part ofthe nitride layer and the oxide layer where a gate will be located andetching the substrate corresponding to the part by a predetermineddepth; (e) forming a second oxide layer over an exposed portion of thesubstrate; (f) implanting ions into the substrate; (g) removing thesecond oxide layer; (h) depositing a gate insulating layer and apolysilicon; (i) polishing until the nitride layer is exposed; (j)removing the nitride layer, depositing an oxide layer conformally anddepositing an nitride layer; (k) etching the nitride layer to form agate sidewall of nitride; (l) implanting ions into the substrate to forma source and drain at both sides of the gate; and (m) removing anexposed oxide layer.

[0016] Although certain example methods have been described herein, thescope of coverage of this patent is not limited thereto. On thecontrary, this patent covers every apparatus, method and article ofmanufacture fairly falling within the scope of the appended claimseither literally or under the doctrine of equivalents.

What is claimed is:
 1. A method for manufacturing a MOSFET device, themethod comprising: (a) selectively forming a shallow trench isolation ina substrate; (b) forming a first oxide layer on a surface of an activeregion of the substrate and implanting ions thereinto for forming a lowdoped drain in the active region; (c) forming a nitride layer; (d)removing a part of the nitride layer and the oxide layer where a gatewill be located and etching the substrate corresponding to the part by apredetermined depth; (e) forming a second oxide layer over an exposedportion of the substrate; (f) implanting ions into the substrate; (g)removing the second oxide layer; (h) depositing a gate insulating layerand a polysilicon; (i) polishing until the nitride layer is exposed; (j)removing the nitride layer, depositing an oxide layer conformally anddepositing an nitride layer; (k) etching the nitride layer to form agate sidewall of nitride; (l) implanting ions into the substrate to forma source and drain at both sides of the gate; and (m) removing anexposed oxide layer.
 2. A method as defined by claim 1, wherein thesubstrate comprises a silicon substrate.
 3. A method as defined by claim1, wherein the shallow trench isolation comprises an oxide layer.
 4. Amethod as defined by claim 1, wherein the predetermined depth is inrange of about 200 to about 1000 angstroms.
 5. A method as defined byclaim 1, wherein the exposed substrate is oxidized at about 600 to about800° C. to form the second oxide layer having a thickness of about 100angstroms in (e).
 6. A method as defined by claim 1, wherein a chemicalmechanical polishing is performed in (i).
 7. A method as defined byclaim 1, wherein the nitride layer is removed by an etch back processingin (k).